EnglishSite MapcontactHome

COEドキュメント

COEドキュメント トップ


■第5回COEワークショップ論文集 2007/1/27 PDF[78MB]
FrontCover PDF[305KB]

BackCover PDF[54KB]

- OPENING SESSION -

[Invited] Technology Challenges for Future CMOS
Masataka Hirose, Director, MIRAI, Advanced Semiconductor Research Center, National Institute of Advanced Industrial Science and Technology

paper PDF[194KB]

slide PDF[3.7MB]

Summary of the 21st Century COE Program on Nanoelectronics for Tera-Bit Information Processing
Atsushi Iwata, COE Leader, Graduate School of Advanced Sciences of the Matter, Research Center for Nanodevices and Systems, Hiroshima University

paper PDF[1.4MB]

slide PDF[3.3MB]

[Invited] Trends and Requirements of Future FETs Based on a Simple Physical Device Model
Dimitri A. Antoniadis and Ali Khakifirooz, Massachusetts Institute of Technology

paper PDF[170KB]

slide PDF[684KB]

- SYSTEM & DEVICE SESSION -
[Invited] Reconfigurable Parallel Image Processing System Using Three-Dimensional LSI
Mitsumasa Koyanagi, Takeaki Sugimura, and Tetsu Tanaka, Tohoku University

paper PDF[813KB]

slide PDF[1.3MB]

Inductor based Circuit Techniques for Chip-to-Chip Interconnect and Standing Wave Clock Generation
Mamoru Sasaki, Bin Yan, Daisuke Arizono, Mitsuru Shiozaki, Atsushi Mori, and Atsushi Iwata, Graduate School of Advanced Sciences of the Matter, Hiroshima University

paper PDF[1.2MB]

slide PDF[1.2MB]

Low-Noise and Low-Voltage Circuit Techniques for CMOS Analog Design
Takeshi Yoshida, Yoshihiro Masui, Mamoru Sasaki, and Atsushi Iwata, Graduate School of Advanced Sciences of the Matter, Hiroshima University

paper PDF[349KB]

slide PDF[630KB]

[Invited] Nanoscale Silicon Devices Using Nanostructure Physics for VLSI Applications
Toshiro Hiramoto, Kousuke Miyaji, and Masaharu Kobayashi, The University of Tokyo

paper PDF[437KB]

slide PDF[1.1MB]

Characterization of Electronic Charged States of Si-based Quantum Dots for Multi-valued MOS Memories
Seiichi Miyazaki, Graduate School of Advanced Sciences of the Matter, Hiroshima University

paper PDF[535KB]

slide PDF[4.0MB]

Formation Techniques for Three-Dimensional MOS Beam-Channel Transistor
Hideo Sunami and Kiyoshi Okuyama, Research Center for Nanodevices and Systems, Hiroshima University

paper PDF[931KB]

slide PDF[2.0MB]

- CIRCUITS & MODELING SESSION -
Functional-Memory Architectures for Information-Processing Systems
Hans Jürgen Mattausch, Tetsushi Koide, M. Anwarul Abedin, and Koh Johguchi, Research Center for Nanodevices and Systems, Hiroshima University

paper PDF[348KB]

slide PDF[532KB]

Functional-Memory-Based Systems Enabling Recognition and Learning
Tetsushi Koide, Hans Jürgen Mattausch, Ali Ahmadi, Takashi Morimoto, and Kousuke Yamaoka, Research Center for Nanodevices and Systems, Hiroshima University

paper PDF[3.2MB]

slide PDF[726KB]

Physics-Based Photodiode Model Enabling Consistent Opto-Electronic Circuit Simulation
Mitiko Miura-Mattausch, Kohkichi Konno, Gaku Suzuki, Tatsuya Ezaki, Osamu Matsushima, Yoshio Mizukane, Dondee Navarro, Masataka Miyake, Norio Sadachika, and Hans Jürgen Mattausch, Graduate School of Advanced Sciences of the Matter, Hiroshima University

paper PDF[21.MB]

slide PDF[541KB]

A Single-chip Gaussian Monocycle Pulse Transmitter using 0.18 μm CMOS Technology for Intra/Interchip UWB Communication
Takamaro Kikkawa, Pran Kanai Saha, Nobuo Sasaki, and Kentaro Kimoto, Research Center for Nanodevices and Systems, Hiroshima University

paper PDF[412KB]

slide PDF[3.0MB]

Optical Interconnection in Silicon LSI
Shin Yokoyama, Yuichiro Tanushi, and Masato Suzuki, Research Center for Nanodevices and Systems, Hiroshima University

paper PDF[3.0KB]

slide PDF[2.5KB]

- DEVICE & PROCESS SESSION -
Ultrarapid Thermal Annealing Induced by DC Arc Discharge Plasma Jet Irradiation
Seiichiro Higashi, Hirotaka Kaku, Tatsuya Okada, Takuya Yorimoto, Hideki Murakami, and Seiichi Miyazaki, Graduate School of Advanced Sciences of the Matter, Hiroshima University

paper PDF[103KB]

slide PDF[2.4MB]

Evaluation of Chemical Structures and Work Function of NiSi near the Interface between NiSi and SiO2
Hideki Murakami, Hiromichi Yoshinaga, Daisuke Azuma, Akio Ohta, Yuuki Munetaka, Seiichiro Higashi, Seiichi Miyazaki, Takayuki Aoyama, Kimihiko Hosaka, and Kentaro Shibahara, Graduate School of Advanced Sciences of the Matter, Hiroshima University

paper PDF[581KB]

slide PDF[2.4MB]

Development of Reliable High-k Gate Dielectrics for Scaled MOSFETs
Anri Nakajima, Research Center for Nanodevices and Systems, Hiroshima University

paper PDF[229KB]

slide PDF[408KB]

Metal Gate and Junction Technologies for Leading Edge Devices
Kentaro Shibahara, Research Center for Nanodevices and Systems, Hiroshima University

paper PDF[1.8MB]

slide PDF[1.4MB]

- POSTER EXHIBITORS -
An Object Detection/Recognition System using a 3-Dimensional Integration with Local and Global Wireless Interconnections
Hiroshi Ando, Seiji Kameda, Nobuo Sasaki, Daisuke Arizono, Kentaro Kimoto, Norimitsu Fuchigami, Kouta Kaya, Mamoru Sasaki, Takamaro Kikkawa, and Atsushi Iwata

paper PDF[2.0MB]

poster PDF[1.5MB]

A Vision System using a 3-Dimensional Integration with Local and Global Wireless Interconnections
Seiji Kameda, Nobuo Sasaki, Hiroshi Ando, Daisuke Arizono, Kentaro Kimoto, Masaki Odahara, Mamoru Sasaki, Takamaro Kikkawa, and Atsushi Iwata

paper PDF[1.3MB]

poster PDF[6.7MB]

Learning Algorithms for Robots Behaving Flexibly in Dynamic Environments
Masahiro Ono, Hiroshi Ando, Mamoru Sasaki, and Atsushi Iwata

paper PDF[431KB]

poster PDF[2.3MB]

Window-based Stereo Matching Algorithm Using a Weighted Average of Costs Aggregated with Window Size Reduction
Kan'ya Sasaki, Seiji Kameda, Hiroshi Ando, Mamoru Sasaki, and Atsushi Iwata

paper PDF[567KB]

poster PDF[89KB]

A 0.6 V Supply CMOS Amplifier Using Noise Reduction Technique of Autozeroing and Chopper Stabilization
Yoshihiro Masui, Takeshi Yoshida, Mamoru Sasaki, and Atsushi Iwata

paper PDF[875KB]

poster PDF[460KB]

Evaluation of Digital Crosstalk Noise to Fully Differential VCO
Akihiro Toya, Yoshitaka Murasaka, Takafumi Ohmoto, and Atsushi Iwata

paper PDF[340KB]

poster PDF[269KB]

HiSIM-SOI: Complete Surface-Potential-Based Fully-Depleted SOI-MOSFET Model for Circuit Simulation
Norio Sadachika, Daisuke Kitamaru, Yasuhito Uetsuji, Dondee Navarro, Marmee Mohd Yusoff, Tatsuya Ezaki, Hans Jürgen Mattausch, Shunsuke Baba, and Mitiko Miura-Mattausch

paper PDF[360KB]

poster PDF[1.3MB]

Photoemission Study of HfO2/Ge(100) Stacked Structures
Hiroshi Nakagawa, Akio Ohta, Hideki Murakami, Seiichiro Higashi, and Seiichi Miyazaki

paper PDF[173KB]

poster PDF[1.2MB]

Photoemission Study of Ultrathin N incorporated Hf-Silicate on Si(100) Systems
Akio Ohta, Hiroshi Nakagawa, Hideki Murakami, Seiichirou Higashi, Seiichi Miyazaki, Seiji Inumiya, and Yasuo Nara

paper PDF[456KB]

poster PDF[3.3KB]

Developement of Fabrication Processes for New SOI MOS Transistor and a Silicidation Technique for Source and Drain of Vertical Channel Devices
Kiyoshi Okuyama, Koji Yoshikawa, Shunpei Matsumura, Atsushi Sugimura, and Hideo Sunami

paper PDF[701KB]

poster PDF[524KB]

A Human-memory Based Learning Model and Hardware Prototyping in FPGA
Ali Ahmadi, M. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide, Yoshinori Shirakawa, and M. Arifin Ritonga

paper PDF[668KB]

poster PDF[1.3MB]

Application of Fully Parallel Associative Memory in Two-stage Pattern Matching
M. Anwarul Abedin, Ali Ahmadi, Yuuki Tanaka, Shogo Sakakibara, Tetsushi Koide, and Hans Jürgen Mattausch

paper PDF[296KB]

poster PDF[617KB]

Highly-Parallel Table-Lookup-Coding with Scalable Architecture using Flexible Multi-Ported Content Addressable Memory
Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, and Hans Jürgen Mattausch

paper PDF[69KB]

poster PDF[570KB]

Multi-Bank Register File for Increased Performance of Highly-Parallel Processors
Koh Johguchi, Ken-ichi Aoyama, Tetsuya Sueyoshi, Moto Maeda, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, and Kazuya Tanigawa

paper PDF[700KB]

poster PDF[2.0MB]

FPGA Implementation of Object-Based Real-Time Object Tracking Architecture
Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Kazutoshi Awane, Tetsushi Koide, and Hans Jürgen Mattausch

paper PDF[93KB]

poster PDF[267KB]

A Single-chip Ultra-Wideband Receiver using Silicon Integrated Antennas for Inter-chip Wireless Interconnection
Nobuo Sasaki, Masashi Fukuda, Masakazu Nitta, Kentaro Kimoto, and Takamaro Kikkawa

paper PDF[698KB]

poster PDF[331KB]

On-Chip Wireless Signal Transmission using Silicon Integrated Antennas
Kentaro Kimoto, Masakazu Nitta, Nobuo Sasaki, and Takamaro Kikkawa

paper PDF[906KB]

poster PDF[330KB]

Workfunction Tuning of NiSi and Pd2Si Fully-Silicided Gates by Predoping
Takuji Hosoi, Kosuke Sano, Masaki Hino, and Kentaro Shibahara

paper PDF[360KB]

poster PDF[359KB]

Ring Resonator Optical Switches for Interconnection on Si Chips
Yuichiro Tanushi and Shin Yokoyama

paper PDF[388KB]

poster PDF[544KB]

Monolithic Mach-Zehnder Optical Modulator Using Electro-Optic Material:(Ba,Sr)TiO3 Film Sputter Deposited at Low Temperature on Silicon
Masato Suzuki, Yuichiro Tanushi, Kazuma Nagata, and Shin Yokoyama

paper PDF[1.0MB]

poster PDF[886KB]

Atomic-Layer-Deposition of HfO2 on Si and Ge Substrates from Hafnium Tetrakis(diethylamino) and Water
Shiyang Zhu and Anri Nakajima

paper PDF[226KB]

このページのトップへ戻る